ESD Electronic Design Automation Checks

Verification of electrostatic discharge (ESD) design rules has grown in volume and complexity as IC designs have become more complex and added significantly more power domains. With each additional power domain, verification of the signals that cross these domains becomes more difficult (particularly in the identification of inadvertent paths), as well as the check of interactions between circuit blocks that may result in many potential ESD discharge current paths [1]. While not strictly related to ESD, designs that incorporate multiple power domain checks are particularly susceptible to subtle design errors that are difficult to identify in the simulation space or with traditional PV techniques. Often, these subtle reliability errors don’t result in immediate part failure, but performance degradation over time. Effects such as Negative Bias Temperature Instability (NBTI) can lead to the threshold voltage of the PMOS transistors increasing over time, resulting in reduced switching speeds for logic gates [2-4], while Hot Carrier Injection (HCI), which alters the threshold voltage of NMOS devices over time, [5] and soft breakdown (SBD) [5] also contribute as time-dependent failure mechanisms, adding to the degradation effects of gate oxide breakdown.